When a processor is in a starting phase, because a quantity of users is relatively small and service types are relatively simple, a statistical packet result obtained by a counter, namely, a count value, is directly stored in an on-chip memory. The on-chip memory is a memory in a chip in which the processor is located, and generally may be a static random access memory (SRAM). An SRAM may have quite high performance.
As a network speed and a quantity of users keep increasing, packet processing performance and capacities of each generation of processors keep increasing rapidly, and a quantity of count values also keeps increasing. Therefore, to meet an increasing capacity requirement, some count values of a same service need to be stored in an on-chip memory, and some other count values need to be stored in an off-chip memory. Generally, an off-chip memory may be a dynamic random access memory (DRAM), and each DRAM includes multiple DRAM banks. The DRAM bank may be understood as a storage space in a DRAM. As being limited by timing parameters such as a time of row cycling (tRC) and a four act win time (tFAW), maximum performance of a DRAM bank can reach only approximately 20 Mops. Currently, in a data storage process, data is generally stored in an order of DRAM banks. When a DRAM bank is full, data is stored in a next DRAM bank. By means of this storage manner, performance of a whole DRAM can reach only approximately 20 Mops.
Therefore, a problem in the prior art is that data storage is slow and inefficient.